1. Field of the Invention
The present invention relates to a semiconductor memory device which is preferably used for SRAMs, etc.
2. Description of the Related Art
Semiconductor memory devices are becoming recently larger in capacity and higher in operation speeds, and are allowing finer designs.
The length of a bit line is therefore increased hereafter, so that an area of a parallel plate between adjacent wirings is increased and hence line capacitance between bit lines is increased.
As illustrated in FIG. 15, a distance between wirings is reduced by making the device further finer, so that line capacitance is increased, but capacitance other than the line capacitance is considered to be oppositely reduced.
In a product of 0.35 .mu.m, when the length of a bit line becomes about 4 mm, line capacitance becomes 0.36 pF.
Although it is further considered that an operation speed of a product is increased and simultaneously multiple bit arrangement is promoted, provided such multiple bit arrangement is achieved, there is required a one-shot pulse generator for each I/O.
In Japanese Laid-Open Patent Application No. Hei11-250670, for example, a system is disclosed in which current consumption is reduced by charging a bit line with electricity using a one-shot pulse only when /WE changes from a high level to a low level and a data input (I/O) changes. The system however requires a one-shot pulse generator circuit for each /WE and for each of all I/Os to result in an increased chip area.
FIG. 5 is a block diagram illustrating a first prior art example of a general SRAM 100. The SRAM 100 includes a 4 transistor-type memory cell array 1, a row address decoder 3 for outputting a word line select signal 101 for selecting a word line of the memory cell data of which is inputted from an address buffer 2, a column address decoder 4 for selecting a bit line, a bit line control circuit 5 for reading/writing memory cell data, an output buffer 6 for outputting memory cell data, a data input buffer 7 for inputting memory cell data, a precharging circuit 8, and an address transition detection circuit 9.
The memory cell array 1 is arranged as illustrated in FIG. 6 .
In the following, operation of the device will be described with reference to FIGS. 6 and 7 in which operation when line capacitance of the bit line is increased, erroneous writing into a memory cell happens.
It is assumed as initial writing electric potential of a memory cell of a memory array that electric potential on the side of D1 of memory cell M2 is at a high level, .cndot.electric potential on the side of /D1, electric potential on the side of D1 of memory cell M2 is at a low level, .cndot.electric potential on the side of D1 is at the high level, electric potential on the side of D2 of memory cell M4 is at the high level, .cndot.electric potential on the side of D2 is at the low level, electric potential on the side of D3 of memory cell M7 is at the low level, .cndot.electric potential on the side of D3 is at the high level, and electric potential on the side of D3 of memory cell M8 is at the high level and .cndot.electric potential on the side of D3 is at the low level.
It is further assumed that a word 1 is selected and is at the high level, and words 2, 3 are in a non-selection state and are at the low level, and further bit lines D2,/D2 are in a selection state with use of a row address decoder circuit.
As illustrated in FIG. 6, a memory cell array becomes a write state from a read state when /WE in FIG. 5 is changed from the high level to the low level.
DB, /DB are changed, whereby bit line D2 is changed from the high level to the low level, and bit line/D2 is changed from the low level to the high level (a state 1 in FIG. 7).
At this time, it is detected bit line D2 is changed from the high level to the low level, and the potential of /D1 becomes further lower from the low level, i.e., it becomes minus owing to line capacitance C2.
Operation of the memory cell M2 at this time will be described with reference to a general memory cell circuit diagram in FIG. 14.
Although electric potential of a gate of N-type transistor Qc in memory cell M2 at is the low level, the potential of /D1 becomes minus and exceeds threshold voltage in a conduction state.
Thereupon, the high level that is initial electric potential on the side of /D1 of memory cell M2 becomes low whereby data is written into memory cell M2 in error. In the same fashion, when data input (DIN) is changed from the low level to the high level, the bit line D2 is changed from the low level to the high level, while the bit line /D2 is changed from the high level to the low level (state 2 in FIG. 7).
In the same time interval the bit line /D2 is changed from the high level to the low level whereby the potential of D3 becomes further lower from than the low level owing to line capacitance C4. Even in this case, data is written in error in memory cell M8 in the same fashion as in the case where /WE is changed from the high level to the low level.
The SRAM as a second prior art, as shown in FIG. 8, includes an error writing protection circuit 10, N-type transistors Q13 to Q20, and a P-type transistor Q21 in addition to the components of the first prior art example illustrated in FIG. 6.
In the following, there will be described a memory cell illustrated in FIG. 8 together with a timing chart illustrated in FIG. 9.
Transistors Q13 to Q20 are very small ones such as those used in memory cells.
Gates and drains of Q13 to Q20 are connected with a drain of Q21, and sources of Q13 to Q20 are connected with each bit line.
For an input signal into Q21 there is used WEB that is the same phase signal as /WE.
The memory cell array becomes a write state from a read state when /WE is changed from the high level to the low level as in the aforesaid first prior art example.
Hereupon, the P-type transistor Q21 becomes conductive with the aid of the WEB signal to charge the drains and gates of N-type transistors Q13 to Q20 with electricity to the high level, and hence N-type transistors Q13 to Q20 become also conductive.
Thereupon, bit lines D1, /D1 to Dn having low electric potential are slightly charged with electricity. In the same time interval DB, /DB are changed to change bit line D2 to the low level from the high level and change bit line /D2 to the high level from the low level (state 1 in FIG. 9).
Hereupon, bit line D2 is changed from the high level to the low level whereby the electric potential /D1 becomes further lower from the low level, i.e., it becomes minus owing to line capacitance C2.
However, bit lines D1, /D1 to Dn, /Dn having low potential are slightly charged with electricity owing to P-type transistor Q21 and N-type transistors Q13 to Q20, so that /D1 is prevented from dropping from 0 V.
When the data input (DIN) changed from the low level to the hi gh level, bit line D2 is changed from the low level to the high level, and bit line /D2 is changed from the high level to the low level.
Since WEB is at the low level, bit lines D1, /D1 to Dn, /Dn having low potential are kept slightly charged with electricity owing to P-type transistor Q21 and N-type transistors Q13 to Q20 (state 2 in FIG. 9).
During the same time interval the bit line /D2 is changed from the high level to a low level whereby the potential of D3 becomes further lower from the low level owing to line capacitance C4.
However, bit lines D1, /D1 to Dn, /Dn having low potential are kept slightly charged with electricity owing to P-type transistor Q21 and N-type transistors Q13 to Q20 as described in the foregoing, so that D3 is prevented from lowering from 0 V.
More specifically, when the memory cell is in a write state, N transistors Q13 to Q20 and P-type transistors Q21 become conductive, and hence any signal is prevented from being written in error by charging the bit lines at low levels with electricity.
However, N-type transistors Q13 to Q20 and P-type transistor Q21 are kept conductive at all times when the memory cells are in a write state, so that a regulated current is conducted through all bit lines that are at the low level to cause large current consumption. 1 M bit products consume about 5 mA ar 5.5 V.
FIG. 11 illustrates an SRAM in Japanese Laid-Open Patent Application No. Hei11-250670 previously described as a third prior art example.
As shown in FIG. 10, this SRAM includes aforesaid error writing protection circuit 10 and the one-shot pulse generator circuit 11 provided additionally to those provided in FIG. 6.
FIG. 12 illustrates the arrangement of the one-shot pulse generation circuit 11. In the following, there will be described the memory cell array illustrated in FIG. 11 together with a timing chart illustrated in FIG. 13.
The one-shot pulse generation circuit 11 generates a one shot pulse (hereinafter, simply referred to as WEQ.) from the one-shot pulse signal WEQ generation circuit 41 illustrated in FIG. 12 when /WE is changed from the read to write state (becomes the low level from the high level).
The one-shot pulse generation circuit 11 further generates a one shot pulse (hereinafter, simply referred to as DEQ.) from one shot pulse signal DEQ generation circuit 42 illustrated in FIG. 12 when the data input signal DIN is changed from the high level to the low level or when the same is changed from the low level to the high level.
In FIG. 11, the error writing protection circuit 10 comprises N-type transistors Q13 to Q20 and P-type transistors Q21, Q22. Gates and drains of Q13 to Q20 are connected with drains of Q21 and Q22, and sources thereof are connected with their spective bit lines. Into the gate of Q21 foregoing WEQ is inputted, and into the gate of Q22 aforesaid DEC is inputted.
In the same manner as the aforesaid prior art example, when /WE is changed from the high level to the row level, the memory cell array becomes the write state from the read state.
Thereupon, a one-shot pulse is generated from aforesaid WEQ generation circuit 41 to charge with electricity the drains and gates of N-type transistors Q13 to Q20 to the high level with the aid of P-type transistor Q21 into a conduction state.
Thereupon, the bit lines of D1, /D1 to Dn, /Dn having low potential are slightly charged with electricity. During the same time interval DB, /DB are changed, whereby bit line D2 is changed from high level to low level while bit line /D2 is changed from low level to high level (state 1 in FIG. 13).
Hereupon, owing to a change of bit line D2 from high to low level the potential of /D1 becomes further lower, i.e., it becomes minus from the low level owing to line capacitance C2.
However, as described previously, bit lines D1, /D1 to Dn, /Dn having low potential have been slightly charged with the aid of the one shot pulse generated from WEQ generation circuit 41, whereby /D1 is prevented from lowering from 0 V.
The time to charge the bit lines with electricity continues only during the time interval the one shot pulse WEQ has been generated, so that no current flows steadily. With the above arrangement, the memory cell can be prevented from being erroneously written without flowing a current steadily with the aid of the line capacitance. A 1 Mbit product consumes a current of about 50 .mu.A at 5.5 V.
Then, when the data input (DIN) is changed from the low level to the high level, bit line D2 is changed from the low level to the high level, while bit line /D2 is changed from the high level to the low level.
At this time a one-shot pulse is generated from aforesaid DEQ generation circuit 42, whereby drains and gates of P-type transistor Q22 and N-type transistors Q13 to Q20 are charged with electricity to the high level into a conduction state.
Thereupon, bit lines of D1, /D1 to Dn, /Dn having low potential are slightly charged ith electricity (state 2 in FIG. 13.). During the same time interval bit line /D2 is changed from high level to low level, whereby the potential D3 becomes further lower from the low level.
However, bit lines D1, /D1 to Dn, /Dn having low potential has been changed slightly owing to the one shot pulse generated from aforesaid DEQ generation circuit 42, D3 can be prevented from lowering from 0 V.
Further, the time to charge the bit lines with electricity continues only during the time interval the one shot pulse DEQ has been generated, so that no current flows steadily.
With the aforesaid arrangement, any memory cell can be prevented from being erroneously written with the aid of line capacitance without flowing a current steadily.
However, such a one-shot pulse generation circuit as illustrated in FIG. 12 is necessary for each /WE and each I/O in order to generate a one shot pulse to result in a large chip area. In the circuit illustrated in FIG. 12, there are needed 12 transistors to generate WEQ and 22 transistors to generate DEQ for both of the P and N-type transistors.
In an 8 I/O product, there are required the sum total of 188 transistors to generate DEQ.
As described above, in the prior art SRAM, a memory cell can be prevented from being written in error owing to line capacitance by providing an error writing protection circuit. Further, a memory cell can be prevented from being written in error owing to line capacitance without flowing a current steadily by providing a one shot pulse generation circuit.
The prior art semiconductor memory device, however, suffers from a difficulty that a circuit scale becomes larger and current consumption is not yet enough reduced.